1. Field of the Invention
The present invention relates to a computer system comprising a processor (CPU) and a bus connection and disconnection function for connecting and disconnecting two buses which are each able to have a bus master.
2. Description of the Prior Art
One of the widely accepted multiple bus master configurations for computer systems is that of the IBM PC/AT, known as the industrial standard architecture (ISA). FIG. 9 is a block diagram showing major components of a conventional computer system that utilizes an ISA multiple bus master configuration. In FIG. 9, reference numeral 101 is a CPU block of the ISA system; 1011 is a CPU; 1012 is a DMA controller; 1013 is a buffer that connects a local bus 1014 of the CPU 1011 with an extended bus (ISA bus) 106 of the ISA system; 1015 is a hold request signal sent by the DMA controller 1012 to the CPU 1011; and 1016 is a hold acknowledge signal returned by the CPU 1011 to the DMA controller 1012. Reference numeral 102 is a request signal DRQx sent from a bus master 107 to the DMA controller 1012, and 103 is an acknowledge signal DACKx returned by the DMA controller 1012 to the bus master 107. With this kind of ISA system, the request signal DRQx 102 generated by the bus master 107 always causes the DMA controller to hold the CPU 1011 before the controller generates the acknowledge signal DACKx 103 that allows the bus master 107 to acquire the bus.
FIG. 10 is a block diagram of a typical prior art bus master. In FIG. 10, reference numeral 301 is a master device that may act as the bus master; 302 is a system interface that interfaces the master device 301 to the system; and 303 is a data buffer provided between a local data bus 307 for the master device and a data bus 313 for the system. Reference numeral 304 is a local address bus for the master device; 305 is a command signal from the master device; 306 is a ready signal to the master device; 308 is an address bus for the system; 309 is a bus acquisition request signal to the system; 310 is a bus acquisition acknowledge signal from the system; 311 is a command signal to the system; 312 is a ready signal from the system; and 314 is a data buffer control signal.
FIG. 11 is a block diagram of the system interface 302 used by the conventional bus master 107. In FIG. 11, reference numeral 320 is a decoding circuit; 321 is a control circuit that generates a control signal; 322 is an interface buffer control circuit; 323a, 323b, etc. are window registers for transferring data from the master device to the system; 324a, 324b, etc. are bank addresses from the window registers 323a, 323b, etc.; 325 is an effective window selection signal; 326 is a multiplexer for effective window selection; 327 is the bank address of the selected window; 328 is an address buffer control signal; 329 is an address buffer; and 330 is a bus acquisition notice signal.
The conventional computer system of the above configuration works as follows. The bus master 107 has within its address space a number of windows for access to the system. The bank addresses of these windows are programmed beforehand in the window registers 323a, 323b, etc. When the master device 301 generates a signal for access to any one of the windows, the decoding circuit 320 decodes the access signal and generates the bus acquisition request signal 309 and window selection signal 325 accordingly. Depending on the content of the window selection signal 325, the multiplexer 326 selects one of the bank addresses 324a, 324b, etc. and outputs the selected bank address 327. Upon receipt of the bus acquisition request signal 309 from the decoding circuit 320, the control circuit 321 turns the ready signal 306 inactive to cause the master device 301 to wait for an access.
When the system allows the bus master 107 to acquire the bus and outputs the bus acquisition acknowledge signal 310 to the latter, the control circuit 321 suitably times the generation of the bus acquisition notice signal 330 and command signal 311. This causes the master device 301 to be accessed on the extended bus of the system. When the device to be accessed is ready to respond, the control circuit 321 receives the ready signal 312 from the system and outputs the ready signal 306 to the master device 301. The interface buffer control circuit 322 controls the data buffer 303 and address buffer 329 in accordance with the command signal 305 from the master device and with the bus acquisition notice signal 330. At the end of the access, the decoding circuit 320 stops outputting the bus acquisition request signal 309. This causes the bus master 107 to release the extended bus of the system and returns control of the extended bus to the system.
FIG. 12 is a block diagram of a prior art bus connection and disconnection device for connecting and disconnecting a slave bus to and from the ISA system. In FIG. 12, reference numeral 1 is a high-order byte data bus constituting part of an ISA bus as a master bus (MBUS); 2 is a low-order byte data bus constituting part of the ISA bus; 3 is an address bus also constituting part of the ISA bus; 4 is a device data width identification signal for use on the ISA bus; 5 is a ready signal for use on the ISA bus; 6 is a command signal for use on the ISA bus; 7 is a high-order byte data bus constituting part of a CPU local bus for the ISA system; and 8 is a low-order byte data bus also constituting part of the CPU local bus.
Reference numeral 11 is a high-order byte data buffer that connects the high-order byte data bus 7 (CPU local bus) with the high-order byte data bus 1 (ISA bus); 12 is a low-order byte data buffer that connects the low-order byte data bus 8 (CPU local bus) with the low-order byte data bus 2 (ISA bus); and 13 is a data swap buffer that swaps data between high-order byte data bus 1 and low-order byte data bus 2. The high-order byte data bus 7, low-order byte data bus 8, high-order byte data buffer 11, low-order byte data buffer 12 and data swap buffer 13 are all included in the CPU block 101 of FIG. 9.
Further in FIG. 12, reference numeral 21 is a high-order byte data bus constituting part of the subordinate bus (SBUS); 22 is a low-order byte data bus constituting part of the subordinate bus; 23 is an address bus also constituting part of the subordinate bus; 24 is a device data width identification signal for use on the subordinate bus; 25 is a ready signal for use on the subordinate bus; 26 is a command signal for use on the subordinate bus; 31 is a high-order byte data buffer that connects the high-order byte data bus 1 (ISA bus) with the high-order byte data bus 21; 32 is a low-order byte data buffer that connects the low-order byte data bus 2 (ISA bus) with the low-order byte data bus 22; and 33 is an address buffer that connects the address bus 3 (ISA bus) with the address bus 23.
Reference numeral 34 is a device data width identification signal conversion circuit that converts the device data width identification signal 24 of the SBUS into the device data width identification signal 4 of the ISA bus; 35 is a ready signal conversion circuit that converts the ready signal 25 of SBUS into the ready signal 5 of the ISA bus; and 36 is a command signal conversion circuit that converts the command signal 6 of the ISA bus into the command signal 26 of the SBUS. Reference numeral 37 is a buffer control circuit that controls the high-order byte data buffer 31 and the low-order byte data buffer 32 in accordance with the address data from the address bus 3 (ISA bus) and with the device data width identification signal 24 and command signal 26 of the SBUS. Reference numeral 38 is a control signal generated by the buffer control circuit 37 for control over the high-order byte data buffer 31 and low-order byte data buffer 32.
The bus connection and disconnection device of the above constitution works as follows. For access to a device on the ISA bus, the ISA system uses the high-order byte data buffer 11, low-order byte data buffer 12 and data swap buffer 13 to access the device that may be either an 8-bit or a 16-bit data width type. Access to the 8-bit device is achieved through the low-order byte data bus 2 (ISA bus) regardless of the access data width or access address. Of the one-time word access cycles generated on the CPU local bus, any one cycle for access to an 8-bit device on the ISA bus is converted to two low-order byte access cycles on the ISA bus before execution.
Where a device on the SBUS connected to the ISA bus is to be accessed, the start of an access cycle on the ISA bus is paralleled by the output of an address signal and a command signal to the SBUS through the address buffer 33 and command signal conversion circuit 36. In response to these signals, the device to be accessed on the SBUS generates the device data width identification signal 24 and ready signal 25. The signals 24 and 25 are converted by the device data width identification signal conversion circuit 34 and ready signal conversion circuit 35 before being sent back to the ISA system. On receiving the returned device data width identification signal 4 and ready signal 5, the ISA system utilizes an effective data byte bus for access. At this point, the buffer control circuit 37 toggles the high-order byte data buffer 31 and low-order byte data buffer 32 to connect the effective data byte bus on the ISA bus side with the SBUS for data transmission.
Another prior art bus connection and disconnection device is disclosed illustratively in Japanese Patent Laid-Open No. HEI/2-50750. The disclosed device comprises a bus conversion starting circuit that detects word access by a 16-bit CPU to an even-number address of 8-bit bus channels; a machine cycle counter that counts CPU clock pulses after getting started by the bus conversion starting circuit; a wait circuit that generates a wait signal for the CPU in response to the output from the machine cycle counter; and a pseudo cycle generation circuit that generates two virtual bus cycles to the 8-bit bus channel determined by the output from the machine cycle counter. One of the disadvantages of the above bus connection and disconnection device is that any device on the SBUS connected to the ISA bus must be an 8-bit type device when accessed by the ISA system.
With prior art ISA computer systems, as described, the CPU must always be put on hold whenever any device on the ISA bus is to be accessed by the multi-bus master. This is an impediment to drawing out the full performance of the system. In a bus connection and disconnection setup, the target device on the SBUS needs to generate the device data width identification signal 4 for the ISA bus in accordance with its bit width. It is impossible to access, on the SBUS, any device whose device data width identification signal 24 fails to coincide in activation timing with the ISA system. Because devices on the SBUS need to respond instantaneously to the access from the ISA system, no bus master can be furnished on the SBUS. Furthermore, the lack of a disconnection request function in the bus master makes it impossible to make full use of the bus disconnection capability of the system. That is, once the bus is acquired, the CPU is always put on hold.